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| KS7308 GENERAL DESCRIPTION FCM(Frequency Conversion Memory) is the high speed line memory that has two 1024X10bits memory banks. KS7308 is designed as low power consumption by CMOS technology. KS7308 is used for camcorder with digital image stabilizer feature. 48-QFP-0707 FCM FEATURES - 1024X10bits 2 bank Line memory. - Independent Read/Write Operation. - Programmable Read Start Address and Write Start Address. - HD Pre-counter for Horizontal blanking. - Serial-Interface Circuit - CMOS Double metal technology - 5V Power supply ORDRING INFORMATION Device KS7308 Package Operating Temperature 48-QFP-0707 0 ~ 70C BLOCK DIAGRAM 10 DIO- DI9 (from A/D) 10 DO0 - DO9 ( to DCP ) WCK (from TG) RCK (from TG) WEN (from TG) HD (from TG) VD (from TG) RSTN(from external) HOE TEST1 TEST2 SCS (from MICOM) SCK (from MICOM) SI (from MICOM) SO (from MICOM) SIO ( Serial I/O ) TOPC ACTO NTTO Momory Bank Momory Control KS7308 PIN DESCRIPTION PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol VDD1 WCK RCK WEN HD VD VDD3 GND3 RSTN SCSN SCK SI SO DO0 DO1 DO2 DO3 DO4 VDD4 GND4 DO5 DO6 DO7 DO8 DO9 HOE NTTO ACTO TOPC VDD5 GND5 TEST0 TEST1 VDD6 GND6 DI9 DI8 DI7 DI6 DI5 DI4 VDD1 GND1 DI3 DI2 DI1 DI0 GND2 I/O I I I I I I I I I O O O O O O O O O O O O O O I I I I I I I I I I I I I Description Power Supply (5V) Memory write clock from TG Memory read clock from TG Memory write enable from TG Horizontal Driving pulse from TG Vertical Driving pulse from TG Power Supply (5V) Ground Reset SIO enable from MICOM SIO clock from MICOM SIO data input from MICOM SIO data output to MICOM Data output bit0 Data output bit1 Data output bit2 Data output bit3 Data output bit4 Power Supply (5V) Ground Data output bit5 Data output bit6 Data output bit7 Data output bit8 Data output bit9 Horizontal odd/even signal output Test output (Vin test) Test output (Vin test) Test input (ACTO control) Power Supply (5V) Ground Test input (Mode control) Test input (Mode) Power Supply (5V) Ground Data input bit9 Data input bit8 Data input bit7 Data input bit6 Data input bit5 Data input bit4 Power supply (5V) Ground Data input bit3 Data input bit2 Data input bit1 Data input bit0 Ground FCM Note vdd5p vdd5i vssi vdd5o vsso vdd vdd5o vdd5p vssp vdd5i vssi vssp KS7308 TEST1 0 0 1 1 TEST0 0 1 0 1 TEST Mode Normal operation Memory Function Test SRAM-A Read/Write Test SRAM-B READ/Write Test FCM PIN ASSIGNMENT T E S T I 33 T E S T 0 32 D I 9 36 D 18 D 17 D 16 D 15 D 14 ADD1 GND1 D 13 D 12 D 11 D 10 GND2 37 38 39 40 41 42 43 44 45 46 47 48 1 V D D 2 G N D 6 35 V D D 34 G N D 5 V D D T O P C 29 A C T O 28 N T T O 27 H O E 26 D O 9 25 24 D O 8 23 D O 7 22 D O 6 21 D O 5 20 G N D 4 31 30 KS7308 19 V D D 4 18 D O 4 17 D O 3 16 D O 2 15 D O 1 14 D O 0 13 S O 2 W C K 3 R C K 4 W E N 5 H D 6 V D 7 V D D 3 8 G N D 3 9 G N D 3 10 S C S N 11 S C K 12 S I KS7308 ABSOLUTE MAXIMUM RATINGS Characteristics Storage temperature Operating temperature Supply voltage Input voltage Symbol Tstg Topr Vdd Vin Rating -40 ~125 0 ~ 70 -0.3 ~ 7.0 -0.3 ~ Vdd +0.3 Unit C C V V FCM ELECTRICAL CHARACTERISTICS (Vdd = 4.75 ~ 5.25V Characteristics Low level input voltage High level input voltage Low level output voltage * 1 Low level output voltage * 2 High level output voltage ** 1, 2 Input Low current Input High current Output leakage current Supply current NOTE : 1 = NTTO,ACTO * 2 = SO, DO [ 9 : 0 ], HOE * Ta = +25C) Min 0.7Vdd 2.4 -10 -10 -10 Typ Max 0.3Vdd 0.4 0.4 +10 +10 +10 40 Unit V V V V V uA uA uA mA Symbol VIL VIH VOL1 VOL2 VOH IIL IIH IOZ Idd Condition IOL = 4mA IOL = 1mA IOH = 1mA Vin = Vss(Gnd) Vin = Vdd Vin = Vdd KS7308 AC ELECTRICAL CHARACTERISTICS FCM tcpw WCK RCK tchp tclp tds tdh DI tac DO Vdd = 5.0 V Characteristics Clock cycle time Clock high time Clock low time Write data hold time Write data set up time Data access time Symbol tcpw tchp tclp tdh tds tac Min 54 20 20 0 10 Max tscy Unit ns ns ns ns ns ns tscy : SCK clock 40 CL = 75pF KS7308 FCM SCSN tshd tscy SCK tscn twl tsds SI twh tsdh tsac tsdft SO Vdd = 5.0 Characteristics Serial clock cycle time Serial clock high time Serial clock low time Serial data hold time Serial data set up time Serial data set access time Serial daa floating time SCSN set up time SCSN hold time Symbol tscy twh twl tsdh tsds tsac tsdft tscn tshd Min 2 700 700 30 30 Max Unit us ns ns ns ns ns ns ns ns Condition 500 20 30 30 KS7308 FCM HD tvdh tvdh VD VD tweh WEN Vdd = 5.0V Characteristics VD level hold time WEN level hold time Symbol tvdh tweh Min 4 5 Max Unit RCK RCK Condition RCL clock RCK clock KS7308 OPERATING FCM FCM has a SIO which is connected to DIS-MICOM. This SIO type can take 4wire type serial commuication with DISMICOM. MICOM can read the status of serial communication error such as parity error and Stop - Byte error. Read start address should contain a zoom value and a motion vecter calculated by DIS -MICOM. FCM starts to out data regarding ot the contents of the read start address resister. Thus, by setting proper read start address, Digital Image Stabilizer can be realized in a hoizontal direction. FCM has a HD precounter also to eliminate unnecessary data count in the memory bank. 1. DATA ACCESS FCM supports normal 4 wired serial interface. The serial data is shifted from the MSB side. There are 6 resisters with 8 bit. These are : (1) SMOD (Serial Mode Resister) (2) Read start address reister (2 Byte) (3) Writer start address resister (2 Byte) (4) HD precounter resister (1 Byte) When user want to change one of above register contents, always user has to provide whole contents of each registers. And STOP Byte should follow. Thus, user has to send total 7 Byte data per each serial communication. For read only status register is valid for normal operation to check SIO operation condition. SI Buffer S P Timing VD Status W Reg R Dec R/W fag KS7308 2. SIO REGISTER [Register diagram] SMOS resister MSB 0 0 0 (lst Byte) 0 RE WE 0 LSB 0 FCM group address RE = 0, WE = 1 : Write enable (Write to register) RE = 1, WE = 0 : Read enable (Read from counter outupt without UD bit) RE = 0, WE = 0 : No operation RE = 1, WE = 1 : Prohibited Read start address register (2 Byte) Defines read start position in the bank memory. MSB 0 MSB A7 A6 A5 0 0 (2nd Byte) 0 (3rd Byte) A4 A3 A2 A1 0 UD A9 LSB A8 LSB A0 UD = 0 : Ciybter increment UD = 1 : Counter decrement Write start address register (2 Byte) Defines write start position in the bank memory MSB 0 MSB A7 A6 A5 0 0 (4th Byte) 0 (5th Byte) A4 A3 A2 A1 0 0 A9 LSB A8 LSB A0 HD control register Control to start read address counter incrementation from rising edge of HD. MSB D7 D6 D5 (6th Byte) D4 D3 D2 D1 LSB D0 Stop Byte MSB 1 1 1 (7th Byte) 0 0 1 0 LSB P P : Even parity KS7308 3. MICOM DATA WRITE FCM (1) First data (SMOD) will entr to S/P buffer from SI for Command decoding. To specify write mode, W - bit has to be set "1" then. FCM is configurated to accept write access from MICOM. (2) 4 Address data and HD control data will be written to Serial buffer. (3) Last data (Stop Byte ) in S/P will be checked such as Stop code and even parity. (4) Data in serial buffer will be transferd to internal register at VD rising edge. [Timing diagram ] SCSN 8 clocks SCK 40 clocks 8 clocks SI 0000W 5 Byte data stop SO 4. MICOM Data Read (1) First data (SMOD) will enter to S/P buffer from SI for Command decoding. To specify read mode, R - bit has to be set "1" then. FCM is configured to accept read operation by driving SO. (2) 4 counter values (Read Address counter ; 2 Byte, Writer Address counter ; 2 Byte,) and HD counter value are read out to SO pin. [Timing diagram ] SCSN 8 clocks SCK 40 clocks Floating area SI 0000R Floating area SO 5Byte data Floating area Floating area refer to Electrical spec KS7308 5. SIO STATUS READ FCM There is one status register to be read out by MICOM. There are 2 bit flags whigh are PE and WF respectivity. The MICOM should check this status to test. (1) Serial communication is successfully completed or not. (2) Setting data are loaded into each register or not. It is up to user to judge this flag or not. [ Timing diagram ] refer to electrical spec SCSN SCK 8 clocks Floating area SI 1111R Floating area SO status Floating area 8 clocks Floating area [ Status register diagram ] MSB ( lst Byte ) 1 1 1 RE WE 0 LSB 0 1 Command group address RE = 1, WE = 0 : Read enable RE = 0, WE = 1 : Prohibited RE = 0, WE = 0 : Prohibited RE = 1, WE = 1 : Prohibited Read data MSB PE WF 0 ( 2nd Byte ) 0 0 0 0 LSB 0 PE : Register write error flag PE = 1 : Error PE = 0 : No Error WF : Register write status flag WF = 1 : Waiting for loading into the register WF = 0 : Loaded KS7308 6. SIO COMMUNICATION PROTOCOL (1) Standard protocol of data write FCM Data write access SCSN should turn High Status read SCSN SCK 56 clocks SMOS / Write data / stop SI Status SO 16 clocks SMOD (2) Invalid write data When user initiate SIO operation before previouse write operation data is loaded into resister at VD timiing, then initial data will be broken. 7. RESET CONDITION The system should supply reset condition by RSTN pin as low level. FCM will initialize each register value as follows. (1) Read/Write address register and Counter is set to "0" (2) HD register is set to "0". (3) SMOD register is set to "0" (4) SO becomes high impedance state. KS7308 PKG DIAGRAM 48-QFP-0707 9.00 _ 0.30 + _ 7.00 + 0.20 FCM Unit : mm 0~ 8 0. 13 + 0.1 - 0.0 0 5 9.00 + 0.30 7.00 + 0.20 # 48 #1 _ 0.18 + 0.10 0.50 0.1 MAX ( 0.75 ) 0.00 MIN 1.40 _ 0.10 + 1.6 MAX 0.50 + 0.20 _ _ 0.10 MAX _ |
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